1. Field of the Invention
This invention relates to a dynamic random access memory (DRAM) and a method for operating the same, and more particularly, to a structure and an operating method for a dynamic random access memory suitable for use as a compatible transistor of a static random access memory (SRAM). The dynamic random access memory is used as the compatible transistor of a static random access memory, that is, a static random access memory with a single transistor.
2. Description of Related Prior Art
A conventional dynamic random access memory comprises a transistor and a capacitor. The area and fabrication cost of the dynamic random access memory is much smaller than those of a static random access memory cell since the conventional static random access memory comprises 4 to 6 transistors. Therefore, to replace the static random access memory with the dynamic random access memory becomes a goal that the industry has endeavored to reach.
However, the data stored in the dynamic random access memory cell has to be refreshed periodically. Such operation is not required for the data stored in the static random access memory. The refresh operation of the dynamic random access memory cell wastes a significant bandwidth of the memory. For example, the clock time of a dynamic random access memory cell operated with a frequency of 100 MHz is 10 nsec. The time for storing a data externally is 10 nsec, and the refresh time is also 10 nsec. The actual refresh time can range from 16 to 500 nsec, depending on the specific circuit design and the capacity of the memory. Thus, the dynamic random access memory has to be idled once for every 500 nsec. The efficiency is consequently dropped to 50-90%. This consideration further reduces the bandwidth of operation.
In the prior art, an attempt for using the dynamic random access memory in the static random access memory has been made. Yet, the property of storing data for a long term has not been achieved since such dynamic random access memory requires an external signal to control the refresh operation. As a consequence, the static random access memory is delayed due to the refresh operation, so the dynamic random access memory is not compatible with the static random access memory.
In other prior art, a high speed static random access memory cache has been used together with a relatively low speed dynamic random access memory to increase the average access time for memory (U.S. Pat. No. 5,559,750). The actual access time for such a structure is dependent on the hit rate of the static random access memory cache, and an additional circuit is required to provide the refresh operation of the dynamic random access memory. Such a structure is still affected by the external access operation, so that a random access time for the integrated structure cannot be achieved.
In another structure, a dynamic random access memory with many memory cell rows is used to reduce the access time of the dynamic random access memory. However, this structure does not allow for the delay of one of the memory cell rows for refresh.
In U.S. Pat. No. 6,028,804, a static random access memory using a dynamic random access memory has been disclosed. An access arbiter is used to arbitrate between the clock required by external access and the generated refresh clock. The clock of the external access has priority in order to avoid a conflict, and it is inevitable that this structure will lose a portion of the operation frequency.